How to update the old version of the IP core in ISE

November 19, 2021

Always open a reminder when opening a project that was previously done in ISE
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the selected IP Block_Memory_Generator v3.1 to a more recent version.
The old version is generated in ISE11.1, now with 12.4, it is recommended to update the IP core. So I groped for a moment and found the following steps:
1. Select the file generated by the IP core in the navigation window.
2. Double-click the manager core in the core generator as shown

How to update the old version of the IP core in ISE

3. Click on the xilinx core generator window that appears, the Update and regenerate... under AcTIons, and then the prompt will appear:
Welcome to Xilinx CORE Generator.
Help system iniTIalized.
Opening project file D:\dul_ram\ipcore_dir\coregen.cgp.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the selected IP Block_Memory_Generator v3.1 to a more recent version.
Project, 'coregen', iniTIalised from file 'D:\dul_ram\ipcore_dir\coregen.cgp'.
Upgrade and regenerate all project IP (latest versions, under current project setTIngs)
Applying current project options...
Finished applying current project options.
Applying current project options...
Finished applying current project options.
Upgrading IP dul_ram to Block Memory Generator version 4.3
Launching upgrade viewer...
Launched upgrade viewer.
Initializing IP model...
Finished initialising IP model.
Generating IP...
WARNING:sim:89 - A core named already exists in the output directory. Output products for this core may be overwritten.
Initializing IP model...
WARNING:sim:602 - The parameter 'Port_B_Write_Rate' is disabled and can't be set to any other value than '0'. Its value will be reset from '50' to its last valid value '0'.
WARNING:sim:192 - Xco Parameter changed from (Port_B_Write_Rate,50) to (Port_B_Write_Rate,0) during Recustomization.
Finished initialising IP model.
XST: HDL Compilation
XST: Design Hierarchy Analysis
XST: HDL Analysis
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
Generating Implementation files.
Generating ISE symbol file...
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1 instead
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
VHDL instantiation template already present, so not regenerating.
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1 instead
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
INFO:sim - Created backup directory D:\dul_ram\ipcore_dirmp\backup_dul_ram\
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.

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