Easy to modify LED light sequence circuit design without processor intervention

August 10, 2019

LED technology is increasingly being applied to our lives. For developers, LEDs or other device sequencers are implemented through a system-on-a-chip (SOC) platform to find a design requirement that reduces costs and reduces design complexity. More and more common. The SOC device integrates the microcontroller functions and various digital peripherals required for a complete LED subsystem on a single chip. This article describes a simple 8 LED light sequence circuit design based on the latest SOC technology. The most exciting part of this design is that the microprocessor does not need to intervene. Rather than using traditional passive digital peripherals interspersed with microcontroller processors, this design is based entirely on the intelligent distributed processing capabilities of SOC digital systems. This frees the central processor from managing the operation of the light sequence circuit, saving CPU resources and making the design more efficient.
This design method can be easily extended to other devices other than LEDs that need to be turned on or off in a specified order, such as sequence timers of different lengths and different modes. There are additional features in this design example:
· 7-bit counter (TC) terminal count
· Instruct the device to turn off the output
· 8-bit output for serial devices
· Clock input to the Verilog state machine
· Bus clock for 8-bit ALU (bit-slice) processor
The development tool used in this article is PSoC Creator, an integrated development environment for Cypress Semiconductor Programmable System-on-Chip (PSoC).
Schematic design
The first step in the design is to create a Verilog symbol to define the input, output, and bit width associated with it (see Figure 1). Once the upper Verilog model (schematic) has been created, it can be used to generate Verilog source files containing pin definitions in all modules. This step does not require the development of functional Verilog code.
Figure 1: Verilog symbol.
The Verilog symbol you just created can now be placed into a high-level schematic design. Here, each input and output can be connected to a clock source, I/O pins, status and control registers, and so on. The high-level principle design of 8-LED lamp sequence circuit is shown in Figure 2.
Figure 2: Example of a high-level design.
Until now, the Verilog symbol has been created, placed in a high-level design, and connected to the device's I/O and clock. Verilog code can now be generated to perform certain functions, in this case the LEDs can be flashed. To manage the logical capabilities of the sequence, a simple data path can be introduced into the design.
This data path contains an 8-bit ALU with a reduced instruction set, two data registers, two accumulators, shift and compare logic, and a 4-deep 8-bit FIFO. To keep the design simple, only two ALUs are used to set the accumulator to 0, and the accumulator is incremented each time the sequence is turned on or off. For more complex sequencing designs, developers can combine multiple ALUs to form a 16-bit or 24-bit processor. Such processors are similar to bit-slice processors, which were popular in the 1970s and early 1980s to provide sufficient processing power for sequential subsystems.
The data path configuration tool is shown below. Note the first two lines of CFGRAM (Configuration RAM): "A0 <- 0", which clears accumulator 0, "A0 <- A0+1", which implements the accumulated value at A0.
Figure 3: Data Path Configuration Tool.
System-on-a-chip (SOC) technology reuses bit-slice technology in a programmable way to intelligently distribute processing tasks to other programmable hardware, reducing the load on the main CPU. Using this method, a standard state machine can be developed. The difference is that usually the algorithm function consumes a large number of logic gates. This is no longer a concern in the new approach, as these functions are implemented in standard standard ALUs, which contain data paths and/or logic controlled by PLD-based state machines.
This design runs independently on the main CPU. The main application can control the light sequence circuit through the API (which can modify the execution parameters). After the light sequence circuit is initialized, the CPU is no longer needed. In addition, this implementation can improve efficiency and use fewer transistors than the CPU method, which can better reduce the overall system power consumption and reserve more resources for other features.
This article discusses the LED light sequence circuit design, the same design method can also be used to similar design, can perform a variety of tasks that require frequent processing through a powerful SOC integrated structure, reducing the main CPU load. Now, engineers are constantly facing a lot of pressure: improving performance, reducing power consumption, and reducing costs... Having a system design tool like this can help engineers continue to create miracles and meet the expectations of the public.

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